1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, referred to as “system LSI”, having a memory and a logic integrated on the same semiconductor substrate. The present invention particularly relates to a test interface circuit for directly accessing a memory externally for testing the memory.
2. Description of the Background Art
In recent years, a DRAM embedded system LSI having a DRAM (dynamic random access memory) and a logic device or a microprocessor integrated on the same semiconductor substrate have been spreading. This DRAM embedded system LSI has the following advantages over a conventional system having a DRAM and a logic device or microprocessor individually mounted on a printed circuit board using soldering or the like.
(1) Since there is no restriction on pin terminals, it is possible to increase the width of the data bus between DRAM and the logic device, to increase data transfer rate and to improve system performance accordingly;
(2) The data bus formed between DRAM and the logic device is on-chip interconnection lines and is smaller in capacitance than an on-board wiring. It is, therefore, possible to decrease operating current in data transfer and to transfer data at high speed; and
(3) Since the system is constituted into a single package, there is no need to provide a data bus wiring and a control signal wiring externally. It is, therefore, possible to decrease the area of the system occupying on the printed circuit board and to make the system small in size.
FIG. 8 is a schematic diagram showing one example of the configuration of a conventional DRAM embedded system LSI. In FIG. 8, DRAM embedded system LSI 500 includes a logic device 502 which performs a predetermined operational processing, a DRAM macro 504 which stores at least data required by logic device 502, and a logic external bus 508 which connects logic device 502 to an external device through a pad group 518.
Logic device 502 may be a dedicated logic device which performs a predetermined operational processing or may be a microprocessor. It suffices that logic device 502 is a circuit device which performs a processing using data stored in DRAM macro 504.
DRAM macro 504 includes a DRAM core 510 which stores data, a test interface circuit (TIC) 512 for directly accessing DRAM core 510 for testing DRAM core 510 externally, and a select circuit 517 which selects one of an internal logic bus 506 of logic device 502 and an internal test bus 516 of test interface circuit 512 for connection to an internal memory bus 515 connected to DRAM core 510. Test interface circuit 512 is coupled to pad group 518 through an external test bus 514.
Each of buses 506, 508, 514, 515 and 516 includes signal lines for transmitting control signals, address signals and data. Since there is no restriction condition due to pin terminals, it is possible to sufficiently increase the width of each of internal logic bus 506, internal memory bus 515 and internal test bus 516. While data read from DRAM core 510 is directly transferred to test interface circuit 512 and logic device 502 without passing through select circuit 517, this internal read data transfer path is not shown in FIG. 8, for simplification of the drawing.
FIG. 9 shows the signals transferred by DRAM core 510 in a list form. In FIG. 9, DRAM core 510 receives, as operation control signals, a clock signal CLK, a clock enable signal CKE which sets an internal clock signal in DRAM core 510 valid/invalid, a row activation signal /ACT which activates internal row select operation, a row deactivation signal /PRE which drives a selected row to an unselected state, an auto-refresh instructing signal /REFA which instructs the refreshing of memory cell data in DRAM core 510, a read operation instructing signal /RE which instructs data read and a write operation instructing signal /WR which instructs data write operation.
Further, DRAM core 510 receives row address signal RA<12:0> of 13 bits and column address signal CA<3:0> of 4 bits for addressing memory cells, a spare row space addressing address signal RAsp for addressing a spare memory cell row, and a spare column space addressing address signal CAsp for addressing a spare column. Spare row space addressing address signal RAsp and spare column space addressing address signal CAsp are used to access a spare memory cell in DRAM core 510, for determining pass/fail of the spare memory cell is in a test performed before defective address fuse programming.
These spare row space addressing address signal RAsp and spare column space addressing address signal CAsp designate a spare memory cell space when set at H level and designate a normal memory cell space when set at L level.
Write data D<127:0> of 128 bits are applied to DRAM core 510 and read data Q<127:0> of 128 bits are outputted from DRAM core 510.
As shown in FIG. 9, DRAM core 510 has a greater number of input/output signals than a general purpose DRAM of a discrete device. Test interface circuit 512 transfers signals/data as shown in FIG. 9 to DRAM core 510 even in test mode of operation. Therefore, when the signals/data shown in FIG. 9 are transferred between test interface circuit 512 and the external tester through external test bus 514 via pad group 518, the number of the pins of the external tester becomes greater than that of these signals/data lines, and test cannot be performed. Further, even if test may be possible, the number of devices which can be measured simultaneously decreases to increase test cost because of the large number of signal/data lines from one device under test.
Test interface circuit 512 is provided to decrease the number of necessary pins during a test, to directly access DRAM core 510 externally and to readily test DRAM core 510.
FIG. 10 shows, in a list form, external signals applied to test interface circuit 512 shown in FIG. 8. The signals shown in FIG. 10 are transferred between the external tester and test interface circuit 512 through external test bus 514 shown in FIG. 8.
In FIG. 10, a test clock signal TCLK and a test clock enable signal TCKE are applied to test interface circuit 512. These test clock signal TCLK and test clock enable signal TCKE are used, respectively, in place of clock signal CLK and clock enable signal CKE used in a normal operation mode.
Further, a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS and a write operation instructing signal /WE are applied to test interface circuit 512. According to combination of logic levels of these control signals ICS, /RAS, /CAS and /WE at, for example, the rising edge of the test clock signal, the operation mode of DRAM core 510 is designated.
Test interface circuit 512 decodes these external control signals, and selectively activates row activation signal /ACT, row deactivation signal /PRE, auto-refresh instructing signal /RFEA, read operation instructing signal /RE and write operation instructing signal /WR shown in FIG. 9 in accordance with the result of decoding.
Address signal AD<12:0> of 13 bits and a spare space addressing address signal ADsp are applied, as address signals, to this test interface circuit 512. A row address and a column address are applied through the same pads (terminals) in time division multiplexedly and spare space addressing address signal ADsp is applied to a spare row and a spare column in time division multiplexedly.
In addition, test write data TD<7:0> of 8 bits, test read data TQ<7:0> of 8 bits and a multi-bit test result output signal TQmbt of 1 bit are transferred, as data, between the external tester and test interface circuit 512. When test date is written, test interface circuit 512 expands the bit width of test data TD<7:0> of 8 bits to data of 128 bits for application to DRAM core 510 through select circuit 517.
When test data is read, test interface circuit 512 sequentially outputs the data of 128 bits read from DRAM core 510 on an 8 bit-by-8 bit basis.
Multi-bit test result output signal TQmbt is a signal which indicates a multi-bit test result with respect to the test read data of 128 bits.
FIG. 11 shows the relationship between the external control signals (TIC control signals) applied to test interface circuit 512 and the DRAM control signals applied to DRAM core 510 in the form of a truth table.
In FIG. 11, the unselected state (DSEL) of DRAM macro 504 is set when chip select signal /CS is at H level. In this state, irrespectively of the logic levels of remaining control signals /RAS, /CAS and /WE, DRAM core 510 is kept in an unselected state.
When chip select signal ICS is set at L level, an operation mode for DRAM core 510 is designated.
In case of a state NOP which indicates no operation mode, control signals /RAS, /CAS and /WE are all set at H level. In this case, the control signals applied to DRAM core 510 are all maintained at H level and a new operation mode is not designated to DRAM core 510. Normally, when this signal NOP is applied, DRAM core 510 is kept in a standby state.
When chip select signal /CS and row address strobe signal /RAS are both set at L level and column address strobe signal /CAS and write operation instructing signal /WE are both set at H level, a state ACT instructing array activation is designated. In this state, row activation signal /ACT is set in an active state of L level for DRAM core 510. The remaining DRAM control signals are kept in an inactive state of H level. Here, the logic levels of the TIC control signals for test interface circuit 512 are determined at the rising edge or falling edge of test clock signal TCLK.
When chip select signal ICS, row address strobe signal /RAS and write operation instructing signal /WE are set at L level and column address strobe signal /CAS is kept at H level, a state PRE instructing precharge operation is designated. In this state, row deactivation signal /PRE is set at L level as the DRAM control signal and DRAM core 510 has the internal state returned to a precharge state.
When chip select signal /CS, row address strobe signal /RAS and column address strobe signal /CAS are set at L level and write operation instructing signal /WE is set at H level, a state REFA instructing refresh operation is designated. In this case, auto-refresh instructing signal /REFA among the DRAM control signals is set at L level and refresh is executed in DRAM core 510.
If chip select signal /CS and column address strobe signal /CAS are both set at L level and row address strobe signal /RAS and write operation instructing signal /WE are both set at H level, then a state RE instructing data read is designated. In this case, read operation instructing signal /RE among the DRAM control signals is set in an active state of L level and the remaining control signals are set at H level.
If chip select signal /CS, column address strobe signal /CAS and write operation instructing signal /WE are set at L level and row address strobe signal /RAS and is set at H level, then a state WE instructing data write is designated. In this state, write operation instructing signal /WR among the DRAM control signals is set at L level.
Test interface circuit 512 converts the TIC control signals into DRAM control signals in accordance with the truth table shown in FIG. 11. Test interface circuit 512 performs address multiplexing, conversion of data bit width and conversion of the control signals, whereby the number of pin terminals which are used when the external tester accesses DRAM core 510 and performs a test operation, can be greatly decreased. Further, since the control signals applied to test interface circuit 512 are the same as those used in a normal clock synchronous type DRAM, the DRAM core 510 can be tested using a tester for a standard clock synchronous DRAM.
FIG. 12 is a schematic diagram showing the configurations of DRAM core 510 and test interface circuit (TIC) 512 shown in FIG. 8. In FIG. 12, for simplification of the drawing, select circuit 517, which is provided between DRAM core 510 and test interface circuit 512, is not shown.
In FIG. 12, DRAM core 510 includes DRAM arrays 550e and 550w each having a plurality of memory cells arranged in rows and columns, and a decoder 552 which selects a memory cell from DRAM arrays 550e and 550w in accordance with an address signal.
In FIG. 12, each of DRAM arrays 550e and 550w has a storage capacity of, for example, 8 M bits. In each of DRAM arrays 550e and 550w, a spare row and a spare column for repairing a fail memory cell are arranged. Decoder 552 includes a row decoder which selects a memory cell row from these DRAM arrays 550e and 550w and a column decoder which selects a memory cell column therefrom.
DRAM core 510 also includes a DRAM data path 556e which inputs and outputs data to and from DRAM array 550e, a DRAM data path 556w which inputs and outputs data to and from DRAM array 550w and a DRAM control circuit 558 which controls the internal operation of DRAM core 510.
Each of DRAM data paths 556e and 556w includes a write driver which transmits internal written data to corresponding DRAM array 550e or 550w, and a preamplifier which amplifies memory cell data read from corresponding DRAM array 550e or 550w. DRAM data path 556e transfers written data WD<127:64> through a write data bus 551e having a 64 bit width and receives 64 bit internal read data RD<127:64> transferred from DRAM array 550e through an internal read data bus 553e. 
While the configuration of DRAM data path 556e will be described later in detail, DRAM data path 556e transfers spare write data SWD<1> through a spare write data line 557e and receives read data SRD<1> from a spare memory cell through a spare read data line 559e when a fail column is repaired. This is because the spare column is simultaneously selected with a normal column in DRAM array 550e. 
Likewise, DRAM data path 556w transfers internal write data WD<63:0> to DRAM array 550w through an internal write data bus 551w having a 64 bit width and receives 64 bit internal read data RD<63:0> from DRAM array 550w through an internal read data bus 553w. In addition, when a fail column is repaired, this DRAM data path 550w receives read data SRD<1> read from the spare column through a spare read data line 559w and transfers data SWD<0> written to the spare column to DRAM array 550w through a spare write data line 557w. 
When a fail column is repaired, DRAM data path 556e substitutes replaces spare write data line 557e for a corresponding internal write data line of internal write data bus 551e and substitutes spare read data line 559e for a corresponding internal read data line of internal read data bus 553e in a normal operation mode. Likewise, DRAM data path 556w replaces a corresponding internal read data line of internal read data bus 553w with spare read data line 559w and replaces a corresponding internal write data line of internal write data bus 551w with spare write data line 557w in a normal operation mode.
On the other hand, in a test mode for repair determination performed before fail address programming for repairing a fail column, the normal memory cells and the spare memory cell are tested and it is examined whether the spare memory cell is normal or pass. In this memory test for repair determination, in DRAM data paths 556e and 556w, spare data lines do not replace the normal data lines, but transfer data to test interface circuit 512, and transfer data with test interface circuit 512.
Test interface circuit 512 includes TIC data paths 560e and 560w which are provided corresponding to DRAM data paths 556e and 556w, respectively, and a TIC control circuit 562 which transfers test data TD<7:0> and TQ<7:0> and multi-bit test result indication signal TQmbt with the external tester.
Although TIC control circuit 562 receives the address signals and the control signals for designating an operation mode as shown in FIG. 10 from the external tester, these signals are not shown in FIG. 12 for simplification of the drawing.
When test data is written, TIC data paths 560e and 560w expand test data TD<7:0> of 8 bits to test data of 64 bits and transfer the expanded test data to DRAM data paths 556e and 556w through corresponding data buses 561e and 561w, respectively.
When data is read, TIC data paths 560e and 560w receive read data of 64 bits from DRAM data paths 556e and 556w through data buses 563e and 563w, respectively.
That is, TIC data path 560e receives data Q<127:64> of 64 bits from DRAM data path 556e through data bus 563e, and also receives spare read data SRD<1> transmitted from spare internal read data line 559e through DRAM data path 556e as spare data SQ<1> through spare read data line 569e. Further, this TIC data path 560e transfers write data D<127:64> of 64 bits to DRAM data path 556e through internal write data bus 561e and also transfers spare write data SD<1> to spare write data line 557e through a spare write data line 567c. 
Likewise, TIC data path 560w receives internal read data Q<63:0> from DRAM data path 556w through read data bus 563w and also receives spare read data SQ<0> through a spare data line 569w. In addition, TIC data path 560w transfers data D<63:0> of 64 bits to DRAM data path 556w through write data bus 561w and also transfers spare write data SD<0> to DRAM data path 556w through a spare write data line 567w. 
TIC control circuit 562 sequentially outputs data of a total of 128 bits applied to TIC data paths 560e and 560w on an 8 bit-by-8 bit basis as test data TQ<7:0>. Further, TIC control circuit 562 transfers signal TQmbt indicating the multi-bit test result of simultaneously read data of 128 bits through a multi-bit signal line 573. If this multi-bit test result indication signal TQmbt indicates non-coincidence, the external tester specifies a fail memory cell in accordance with test read data TQ<7:0> and expected value data.
FIG. 13 is a schematic diagram showing the configuration of a main portion of DRAM arrays 550e and 550w. Since DRAM arrays 550e and 550w have the same configuration, FIG. 13 representatively shows one DRAM array 550.
In FIG. 13, DRAM array 550 includes normal memory cells NMC arranged in rows and columns and spare memory cells SMC for repairing a fail normal memory cell. Spare memory cells SMC are also arranged in rows and columns. Normal memory cells NMC and spare memory cells SMC are arranged being aligned in a row direction. It is noted, however, that FIG. 13 representatively shows one normal memory cell NMC and one spare memory cell SMC.
A word line WL is arranged corresponding to normal memory cells NMC and spare memory cells SMC aligned in a row direction. A word line select signal is transmitted to word line WL from a row decoder not shown. A pair of normal bit lines NBL and /NBL are arranged corresponding to each column of normal memory cells NMC. Likewise, a pair of spare bit lines SBL and /SBL are arranged corresponding to each column of spare memory cells SMC. In FIG. 13, only bit lines NBL and SBL are shown.
Internal read data lines RDL0 to RDL63 and internal write data lines WDL0 to WDL63 are arranged extending in a column direction, one for each predetermined number of bit line pairs. A spare read data line SRDL and an internal spare write data line SWDL are arranged extending in the column direction in correspondence to spare memory cells SMC.
To select a memory cell column, a write column select line WCSL which transmits a write column select signal in data write mode and a read column select line RCSL which transmits a column select signal in data read mode are arranged extending in the row direction. Write column select line WCSL makes a write column select gate WSG arranged on normal bit line NBL conductive to connect normal bit line NBL to corresponding internal write data line WDL. Further, when data is read, normal bit line NBL is connected to internal read data line RDL through a read column select gate RSG in accordance with a signal on read column select line RCSL. In FIG. 13, read column select gate RSG and write column select gate WSG provided corresponding to internal read data line RDL0 and internal write data line WDL0, respectively are representatively shown.
Normally, read column select gate RSG has a differential amplification gate structure. When selected, read column select gate RSG reads a signal on the corresponding bit line (pair) to the internal read data lines (pair) by MOS transistors (insulated gate field effect transistors) having the gates connected to the corresponding bit lines.
Likewise, a spare write column select gate SWSG which connects spare bit line SBL to spare write data line SWDL in accordance with a select signal on write column select line WCSL, and a read column select gate SRSG which connects spare bit line SBL to internal spare read data line SRDL in accordance with a column select signal on read column select line RCSL are provided corresponding to spare bit line SBL.
Since column select lines WCSL and RCSL are arranged extending in the row direction, a normal memory cell and a spare memory cell are always selected simultaneously and memory cell data are transmitted to internal read data lines RDL0 to RDL63 and spare read data line SRDL or to internal write data lines WDL0 to WDL63 and spare write data line SWDL.
FIG. 14 is a schematic diagram showing the arrangement of sense amplifiers for one write data line and one read data line. In FIG. 14, a sense amplifier group SAG which includes 16 sense amplifiers are arranged for internal read data line RDL and internal write data line WDL. One of the 16 sense amplifiers included in sense amplifier group SAG is selected by column address CA<3:0> of 4 bits. Accordingly, 16 columns of spare memory cells SMC are provided per spare data line. Each sense amplifier is arranged to correspond to each bit line pair. When activated, the sense amplifier senses, amplifies and latches memory cell data on a corresponding bit line.
Normally, this DRAM array 550 is divided into 16 row blocks. In each row block, 512 word lines are arranged. One word line is selected in one row block by row address RA<12:0> of 13 bits. To repair a fail memory cell row, a spare row is also arranged. As the arrangement of this spare row, a spare word line may be arranged in each row block or spare word lines may be arranged collectively in a specific row block.
FIG. 15 is a schematic diagram showing correspondence in fail column repair. In FIG. 15, one DRAM array is divided into a plurality of row blocks. In FIG. 15, two row blocks RBi and RBj are shown. In the DRAM array, internal read data lines RDL0 to RDL63, internal write data lines WDL0 to WDL63, spare read data line SRDDL and spare write data line SWDL are arranged, commonly to the row blocks, extending in the column direction.
In row block RBi, if a memory cell related to internal read data line RDLa and internal write data line WDLa is a fail cell, internal read data line RDLa and internal write data line WDLa are replaced by spare read and write data lines SRDL and SWDL, respectively. In row block RBj, if a memory cell related to internal read data line RDLb and internal write data line WDLb is a fail cell, internal read data line RDLb and internal write data line WDLb are replaced by spare read data lines SRDL and spare write data line SWDL, respectively.
Therefore, when a row block is specified, the internal read data line or internal write data line to be replaced is uniquely determined. By repairing a fail column in units of internal data lines, even if the column select lines, i.e., the write column select line and read column select line are extended in the row direction and a spare memory cell and a normal memory cell are selected simultaneously, it is possible to accurately perform redundancy replacement to repair a fail memory cell.
FIG. 16 is a schematic diagram showing the configuration of DRAM data paths 556e and 556w shown in FIG. 12. Since DRAM read data paths 556e and 556w have the same configuration, DRAM read data path 556 is shown in FIG. 16 as a representative of DRAM data paths 556e and 556w. 
In FIG. 16, DRAM read data path 556 includes preamplifiers PA0 to PA63 provided corresponding to internal read data lines RDL0 to RDL63, respectively, write drivers WV0 to WV63 arranged corresponding to internal write data lines WDL0 to WDL63, respectively, a spare preamplifier SPA arranged corresponding to spare read data line SRDL, and a spare word driver SWV arranged corresponding to spare write data line SWDL.
These preamplifiers PA0 to PA63 and SPA are simultaneously activated by a control circuit (TIC control circuit) which is not shown in FIG. 16. Write drivers WV0 to WV63 and SWV are also activated concurrently by the control circuit (TIC control circuit), not shown, in data writing. If no redundancy replacement is performed, spare write driver SWV may be kept inactive.
DRAM read data path 556 further includes a redundancy control circuit CRC which generates a redundancy replacement select signal in accordance with a spare column check test mode instructing signal SPCC and a row block address RB, multiplexers (MUX) MX0 to MX63, provided corresponding to preamplifiers PA0 to PA63, for selecting one of each respective output data from corresponding preamplifiers PA0 to PA63 and output data from spare preamplifier SPA in accordance with select signals RSEL0 to RSEL63 from redundancy control circuit CRC, read data latches RLH0 to RLH63 which latch and transfer the output data of multiplexers MX0 to MX63, respectively, and output buffers OBF0 to OBF63 which buffer the output data of read data latches RLH0 to RLH63 and generate read data Q0 to Q63, respectively.
This spare column check test mode instructing signal SPCC is activated in a memory test for spare determination performed before the programming of a fail memory cell address.
When spare column check test mode instructing signal SPCC is deactivated, redundancy control circuit CRC generates read select signals RSEL0 to RSEL63 so as to replace a fail read data line programmed for each row block by a spare read data line in accordance with row block address RB.
When spare column check test mode instructing signal SPCC is activated, redundancy control circuit CRC sets all of select signals RSEL0 to RSEL63 into an inactive state to cause multiplexers MX0 to MX63 to select the output data of corresponding preamplifiers PA0 to PA63, respectively.
Further, DRAM data path 556 includes a spare read data latch SRLH which latches and transfers the output data of spare preamplifier SPA in accordance with a clock signal, not shown, when a test mode instructing signal TE is activated, and a spare output buffer SOBF which buffers the output data of spare read data latch SRLH to generate spare read data SQ. The output state of spare read data latch SRLH may be set so as to set spare output buffer SOBF in an output high impedance state when spare column check test mode instructing signal SPCC is inactivated. Alternatively, spare output buffer SOBF may be set in an output high impedance state when spare column check test mode instructing signal SPCC is inactivated.
DRAM data path 556 further includes input buffers IBF0 to IBF63 which are provided corresponding to write data bits D0 to D63, respectively, write data latch WLH0 to WLH63, provided corresponding to input buffers IBF0 to IBF63, for latching the output data bits of corresponding input buffers IBF0 to IBF63 in accordance with a clock signal, not shown, to transfer the output data bits to corresponding write drivers WV0 to WV63, respectively, a multiplexer MX70 which selects one of the output data bits of input buffers IBF0 to IBF63 in accordance with select signals WSEL0 to WSEL63 from redundancy control circuit CRC, respectively, a multiplexer MX71 which selects one of the output data of multiplexer MX70 and the output data of spare input buffer SIBF in accordance with spare column check test mode instructing signal SPCC, and a spare write data latch SWLH which latches the output data of multiplexer MX71 in accordance with a clock signal, not shown, and transfers the latched data to spare write driver SWV.
When spare column check test mode instructing signal SPCC is inactive, multiplexer MX71 selects the output data of multiplexer MX70 and transfers the selected output data to spare write data latch SWLH. When spare column check test mode instructing signal SPCC is activated, multiplexer MX71 selects the output data of spare input buffer SIBF for transference to spare write data latch SWLH. When spare column check test mode instructing signal SPCC is deactivated, this spare input buffer SIBF may be set in an output high impedance state.
In a normal operation mode, DRAM data path 556 performs redundancy replacement (data line replacement) for repairing a fail column under the control of redundancy control circuit CRC. That is, in data read, the output data of the preamplifier corresponding to a fail read data line is replaced by the output data of spare amplifier SPA by multiplexers MX0 to MX63. In data write, the write data transferred to this fail write data line is transferred to spare write data latch SWLH by multiplexers MX70 and MX71 and transferred onto spare write data line SWDL by spare write driver SWV. In this case, although data is written to a fail column as well, no problem occurs because the fail read data line corresponding to the fail memory cell is replaced by the spare read data line.
Further, a case may be possibly considered where no redundancy replacement is performed, multiplexer MX70 does not select data and spare write driver SWV writes invalid data to a spare memory cell. Even in this case, when this row block is accessed, even if invalid data is written to the spare memory cell, no problem occurs because redundancy replacement is not performed.
In a test operation mode for spare determination performed before fail address programming, redundancy control circuit CRC sets all of select signals RSEL0 to RSEL63 in an inactive state and causes multiplexers MX0 to MX63 to select the output data of corresponding preamplifiers PA0 to PA63, respectively. In addition, in this test operation mode for repair determination, spare read data latch SRLH is activated, the output data of spare amplifier SPA is transferred and spare read data SQ is generated by spare output buffer SOBF.
Likewise, in this test operation mode for repair determination, input data SD of spare input buffer SIBF is selected by multiplexer MX71 and transferred to spare write driver SRV through spare write data latch SWLH. In the test operation mode for repair determination, therefore, it is possible to directly access the spare read data line and the spare write data line externally.
FIG. 17 is a schematic diagram showing the configuration of a part related to data write in TIC data paths 556e and 556w shown in FIG. 12. In FIG. 17, the configuration of a part for generating write data in TIC control circuit 562 is also shown. TIC control circuit 562 includes a cycle shift circuit 600 which transfers test data TD<7:0> of 8 bits in accordance with test clock signal TCLK. This cycle shift circuit 600 delays applied test data TD<7:0> by a predetermined cycle period of test clock signal TCLK and outputs test data TD<7:0>.
In addition, address signals AD<12:0> of 13 bits and spare address space addressing address signal ADsp are applied to TIC control circuit 562.
Data Df<7:0> of 8 bits synchronized with test clock signal TCLK is generated from this cycle shift circuit 600.
TIC data path 560e includes drive circuits DRE0 to DRE7 each of which copies data Df<7:0> and generates 8-bit data, and a driver SDRe which copies data Df<7> and generates spare data SD<1>. Drive circuits DRE0 to DRE7 include drivers of 8 bits for generating data of 8 bits, i.e., D<64:71>, D<72:79>, . . . and <120:127>, respectively. Therefore, each of 8-bit data D<64:71>, D<72:79>, . . . and <120:127> has the same data pattern as that of data Df<7:0>.
Likewise, TIC data path 560w includes drive circuits DRW0 to DRW7 which copy data Df<7:0> and each generate 8-bit data, and a driver SDRw which copies data Df<7> and generates spare data SD<1>. Drive circuits DRW0 to DRW7 generate data of 8 bits, i.e., D<7:0>, D<15:8>, . . . and <63:56>, respectively. Each of the 8-bit data generated by data path 560w has the same data pattern.
Here, the data pattern of test data TD<7:0> is expanded to data of 128 bits so as to satisfy the following conditions.
D<8·n+m>=TD<m>, where n is an integer from 0 to 15 and m is an integer from 0 to 7.
Each of TIC data paths 560e and 560w copies data Df<7:0>, whereby 128-bit data can be generated from the 8-bit data and transmitted to DRAM core 510 and spare write data SD<0> and SD<1> can be transferred to DRAM core 510 as well.
FIG. 18 is a schematic diagram showing the configurations of data read sections of TIC data paths 560e and 560w shown in FIG. 12. Since TIC data paths 560e and 560w have the same configuration, the configuration of TIC data path 560w is specifically shown and that of TIC data path 560e is simply shown by blocks in FIG. 18.
TIC data path 560w includes unit processing circuits UPW0 to UPW7 which are arranged corresponding to 8-bit data Q<7:0> to Q<63:56>, respectively, and a tri-state buffer 600w which is provided corresponding to spare read data SQ<0>.
Unit processing circuits UPW0 to UPW7 have the same configuration, and each includes a tri-state buffer 610 which buffers corresponding 8-bit data Q and generates internal data TQf<7:0> when activated, and a comparison circuit 612 which compares corresponding internal read data Q with expected value data CMPD<7:0>, compresses the comparison result to data of 1 bit and outputs the compressed 1-bit data.
Tri-state buffer circuit 610 is activated in accordance with corresponding select signal QSEL among select signals QSEL<15:0>generated in accordance with an address signal from TIC control circuit 562. Tri-state buffer 600w is selectively activated in accordance with a select signal SQSEL<0> from TIC control circuit 562.
TIC data path 560e includes tri-state buffer circuit 600e provided corresponding to spare data SQ<1> and unit processing circuits UPE0 to UPE7 provided corresponding to 8-bit data Q<64:71> to Q<120:127>, respectively. Unit processing circuits UPE0 to UPE7 are selectively activated in accordance with corresponding select signals QSEL<15:0>, respectively, as in the case of unit processing circuits UPW0 to UPW7.
Each of unit processing circuits UPE0 to UPE7 includes a tri-state buffer circuit which buffers corresponding 8-bit data and generates internal read data TQf<7:0> when activated, and a comparison circuit 612 which performs a multi-bit test to indicate whether expected value data CMPD<7:0> is consistent with the respective data bits.
Comparison circuit 612 compares 8-bit expected value data CMPD<7:0> with corresponding 8-bit data D<8·n+7:8·n> on a bit by bit basis and compresses the 8-bit signal obtained by bit-by-bit comparison to a 1-bit signal Qbtf<n>. 16-bit signal Qmbtf<15:0> indicating the comparison result from comparison circuit 612 are further compressed by TIC control circuit 562, and a 1-bit multi-bit result indication signal TQmbt is generated and transferred to the external tester. In the compression, it is merely determined whether the logic level of each bit of 16-bit signal Qmbtf<15:0> indicates a normal state (AND processing is performed).
FIG. 19 is a schematic diagram showing the configuration of a part for generating the select signals in TIC control circuit 562 shown in FIG. 18. In FIG. 19, TIC control circuit 562 includes a flip-flop 620 which transfers address signal AD<12:0> and the spare space addressing signal ADsp synchronously with test clock signal TCLK an generates internal signals intAD<12:0> and intADsp, a flip-flop 621 which further transfers internal address signals intAD<12:0> and intADsp from flip-flop 620 synchronously with test clock signal TCLK and generates row address signal RA<12:0> and spare row space addressing address signal RAsp, a flip-flop 622 which transfers address signal intAD<3:0> of 4 bits from flip-flop 620 synchronously with test clock signal TCLK and generates column address signal CA<3:0>, cascaded flip-flops 623 to 625 of three stages which transfer internal address signals intAD<9:6> of 4 bits and intADsp from flip-flop 620 synchronously with test clock signal TCLK, and a decoder 626 which decodes the output signal of flip-flop 625 and generates select signals QSEL<15:0> and SQSEL<1:0>.
The reason for using three flip-flops 623 to 625 at a preceding stage of decoder 626 is to delay the output signal of this decoder 626 by a time period corresponding to latency in reading of bit data. This latency indicates the time period (clock cycle) required since a read operation instructing signal instructing data read is applied from test interface circuit 512 to DRAM core 510 until test data is read from DRAM core 510 and transferred to test interface circuit 512. Here, latency is assumed 2 (two clock cycles).
Each of flip-flops 620 to 625 outputs a signal synchronously with the rise of test clock signal TCLK.
FIG. 20 is a timing chart representing the operation of DRAM macro 504 shown in FIGS. 12 to 19 when test data is read. The test data read operation of this DRAM macro will now be described with reference to FIG. 20.
Test interface circuit (TIC) 512 delays control signals externally applied by one clock cycle of test clock signal TCLK and transfers the delayed control signals to DRAM core 510. Accordingly, DRAM core 510 takes in the control signals and address signals at the rise of test clock signal TCLK two clock cycles after when the control signals and the others are applied from the tester to test interface circuit 512, and executes internal operation. In FIG. 20, clock signal CLK and test clock signal TCLK applied to DRAM core 510 are assumed the same in waveform.
At time T1, control signals representing row activation instructing signal ACT are applied to test interface circuit 512 and also row address signal RA(k) of 13 bits are applied to test interface circuit 512. Test interface circuit TIC 512 decodes the control signals applied externally and transfers the row activation instructing signal ACT to DRAM core 510 in accordance with the decoding result, synchronously with the rise of clock signal TCLK. As shown in FIG. 19, at this time, row address signal RA(k) is also transferred synchronously with the rise of test clock signal TCLK.
DRAM core 510 takes in row activation instructing signal ACT as well as row address signal RA(k) synchronously with the rise of clock signal CLK at time T3 and executes an internal row select operation.
Next, at time T2, a write operation instructing signal instructing data write as well as column address signal CA(m) and test data TD(m) is applied to test interface circuit TIC 512. Test interface circuit TIC 512 takes in the control signals, column address signals and test data synchronously with the rise of test clock signal TCLK, performs internal control signal decoding operation, and transfers write operation instructing signal WRITE, column address signal CA(m) and test data D(m) for DRAM core 510 to DRAM core 510 synchronously with the rise of clock signal TCLK at time T3.
DRAM core 510 takes in write operation instructing signal WRITE, column address signal CA(m) and data D(m) synchronously with the rise of clock signal CLK at time T4, executes column select operation and writes data D(m) of 128 bits to columns designated by column address signal CA(m).
At time T3, a command (READ) representing data read as well as column address signals CA(n) and test data TD(n) are applied to test interface circuit TIC 512. Test data TD(n) in data read is used as expected value data CLPD<7:0> to be compared by the data paths of test interface circuit TIC 512.
Test data TD(n) applied to test interface circuit TIC 512 at time T3, is not transferred to DRAM core 510 since TIC data paths do not execute write operation. In the timings shown in FIG. 20, in particular, comparison data are generated by shifting externally applied data by a predetermined cycle period in view of column latency in data write and then applied to the internal comparison circuit. In this case, therefore, when comparison data is inputted, write data written in response to the write command is already transferred internally and then transferred to DRAM core 510. As a result, no problem occurs even if write data as well as the read command is applied to test interface circuit TIC 512.
It is noted, however, if it is required to input comparison data at an earlier cycle than that of the application of the read command because of the restriction of the number of stages of delays for generating comparison data internally, a restriction that the write operation cannot be performed on this comparison data inputted, or other occurs.
A command (READ) applied to test interface circuit TIC 512 at time T3 is decoded by test interface circuit TIC 512, read operation instructing signal READ is generated, and read operation instructing signal READ and column address signal CA(n) are applied to DRAM core 510 synchronously with the rise of test clock signal TCLK at time T4. Here, the command instructs an operation mode by a combination of a plurality of control signals.
DRAM core 510 performs a column select operation in accordance with read operation instructing signal READ and column address signal CA(n) synchronously with the rising edge of clock signal TCLK at time T5, and reads test data internally.
At time T4, control signals (PRE) representing precharge operation are applied to test interface circuit TIC 512 and decoded by test interface circuit TIC 512, and row deactivation instructing signal PRE is transferred to DRAM core 510. At time T6, DRAM core 510 executes internally precharge operation.
DRAM core 510, which has column latency of 2 cycles, reads the data read internally in accordance with read operation instructing signal READ applied at time T5 in a clock cycle starting at time T6, and applies read data Q(n) to test interface circuit TIC 512 at time T7.
In test interface circuit 512, 8-bit data is generated from 128-bit data Q(n) transferred from DRAM core 510 in the clock cycle starting at time T6 in accordance with the select signals from decoder 626 shown in FIG. 19, data TQ(n) taken in at time T3 is compared with the read data by the comparison circuits and the signals indicating the comparison results are generated by time T7. In a clock cycle starting at this time T7, test interface circuit TIC 512 outputs 8-bit test data TQ(n) as well as multi-bit test result indication signal Qmbt(n).
Decoder 626 and flip-flops 620 to 625 shown in FIG. 19 constantly operate synchronously with test clock signal TCLK. Accordingly, by sequentially applying address signals intAD<9:6> and ADsp shown in FIG. 19 in respective clock cycles, 8-bit data is sequentially selected according to select signals QSEL<15:0> and SQSEL<1:0> outputted from decoder 626 and read from test interface circuit TIC 512.
The external tester compares 8-bit test data TD(n) with test read data TQ(n) bit by bit when multi-bit test result indication signal Qmbt(n) indicates the non-coincidence, and specifies the location of a fail memory cell. If multi-bit test instructing signal Qmbt(n) indicates coincidence, each bit of 8-bit test data TQ(n) is determined to be normal. As a result, the external tester is not required to specify the location of the fail memory cell for each 8-bit test data, thereby shortening test time.
FIG. 21 is a schematic diagram showing the configuration of a part related to spare read data bits in test interface circuit TIC 512. Since TIC data paths 560e and 560w have the same configuration for spare read data SQ<1> and SQ<0>, respectively, spare read data SQ in one TIC read data path 560 is representatively shown for TIC data paths 560e and 560w in FIG. 21.
In FIG. 21, a spare read data bit processing section includes tri-state buffer 600 which receives spare data bit SQ from the corresponding DRAM data path, and tri-state buffers FDR6 to FDR0 each supplied with a power supply voltage VCC as an input. Tri-state buffers 600 and FDR6 to FDR0 are activated when spare select signal SQSEL is activated and generate internal data TQf<7> to TQf<0>, respectively when activated.
Therefore, if spare data bits are read externally through test interface circuit TIC 512 in a memory test for repair determination, 7-bit data TQ<6:0> having each bit fixed to H level is outputted together with spare data bit TQ<7>. No multi-bit test is performed on the spare data bit because the spare data bit is data of one bit.
If the spare data bit is read together with the other fixed data and applied to the external tester, such a problem arises that the test cannot be performed while successively accessing a spare column address space and a normal column address space, as will be described in the following.
FIG. 22 is a schematic diagram showing the mapping of a fail bit memory in the external tester. This fail bit memory is provided in the tester, and stores pass/fail information on the memory cells of DRAM core 510 bit by bit (for each memory cell). In the fail bit memory, a fail memory cell is identified for fuse blowing for fail address programming and it is also determined whether the fail memory cell can be repaired. In this determination, it is determined whether or not there is a fail row/column and whether or not the fail row/column can be repaired based on the data stored in the fail bit memory.
In FIG. 22, in fail bit memory 650, row addressing is made by address RA<12:0> and spare row address space addressing address signal RAsp in the row direction and column addressing is made by address AD<9:6>, test data TQ<7:0>, spare address space addressing address signal ADsp and column addresses CA<3:0> in the column direction. By way of example, FIG. 22 shows that data group TUG of 136 bits is designated in fail bit memory 650 by column address CA<3:0> in the column direction.
If the spare column address space is designated continuously with the normal column address space as shown in FIG. 22, normal memory cell data groups NQG each formed of 8 bits and spare memory cell data groups SQG each formed of 8 bits are continuously arranged as shown in FIG. 23. The data bits may be mapped according to data terminals and these bits of 8-bit data may be stored in a distributed manner.
In the region of normal memory cell data group NQG, each of the 8-bit memory cells stores data indicating pass/fail. In spare memory cell data group SQG, memory cells corresponding to the 7-bit H-fixed data region each store fail bits F, as shown in FIG. 24. In a spare memory cell region which stores spare data bit SQ, a pass/fail bit P/F is stored in accordance with the coincidence/non-coincidence with the expected value data.
If a test is performed using various test data patterns, fail bits F are stored in the spare column address region of these 7-bit memory cells because expected value data CMPD has various patterns different from that of H-fixed data. Upon determination on whether or not a fail cell can be repaired, this repair determination is made in accordance with the distribution of fail bits. Therefore, if such fail bits are stored in the spare column address space, the entire of the spare column address region is always determined to be fail and the repair determination cannot be accurately made. If pass/fail bit information is disposed in a distributed manner in this fail/bit memory in accordance with the test terminals, in particular, fail bits F are distributed in accordance with the respective terminals and mixed with data for the normal memory cells, making it even more difficult to specify a fail memory cell.
To prevent fail bit F from being stored in the spare column address region, it is necessary to take the following measures in the tester. Specifically, in the tester, a comparison circuit which determines whether the data transferred from the test interface circuit is consistent with the expected value is isolated from the test terminals when the spare data bits are transferred, so that the fail bit information can not be stored in the fail bit memory. The changeover of the connection of the test terminals to the comparison circuits cannot be executed at real time while a test is performed with various test patterns being generated. In this case, one possible solution may be considered to provide the following configuration in the tester.
FIG. 25 shows one example of the possible configuration of this external tester. In FIG. 25, the external tester includes a register 660 which stores expected value data TD, a comparison circuit 662 which compares the expected value data from register 660 with test read data TQ<7:0> of 8 bits applied from test interface circuit 512, and a selector 664 which selects one of the output signal of lower 7 bits of comparison circuit 662 and power supply voltage VCC level in accordance with spare address space addressing address signal ADsp. The 8-bit data selected by selector 664 is written to fail bit memory 650.
In case of the arrangement shown in FIG. 25, if a spare address is designated and data is read from the spare address, selector 664 sets data TQ<6:0> of lower 7 bits at power supply voltage VCC level which indicates a pass state irrespectively of the logic level of the output signal of comparison circuit 662. Then the comparison result of data TQ<7> corresponding to the spare data bit as well as the output bits of this selector 664 are written to fail bit memory 650. In this case, therefore, data is written to fail bit memory 650 in a unit of 8 bits, the data is set in a pass/fail state in accordance with the comparison result for the spare data and the other data are all set in a pass state, making it possible to detect the fail bit of the spare memory cell. Further, unnecessary fail bits are not stored in a distributed manner in fail bit memory 650, it is possible to accurately make repair determination in accordance with the distribution of fail bits stored in fail bit memory 650.
In case of the arrangement shown in FIG. 25, however, the connection path of selector 664 is changed in accordance with spare space addressing address signal ADsp to change over the output signals of comparison circuit 662. If the transmission path of the output signals of comparison circuit 662 is changed over using address signal ADsp for spare space addressing, it takes time to transmit the output signals of comparison circuit 662 to fail memory 650, making it impossible to write the result of test data of test interface circuit 512 which operates synchronously with a high speed clock at real time.
Further, in this case, the address signal ADsp for spare space addressing is generated in the tester. Therefore, it is necessary to change the state of the address signal ADsp for spare space addressing in accordance with the timing of the spare memory cell data transferred from test interface circuit 512 and to consider a timing margin between these signals. Thus, high speed operation cannot be ensured and data indicating the pass/fail state of the spare memory cell cannot be stored at real time.
Moreover, to arrange the selector used only in a memory test for repair determination in the tester, it is necessary to modify the tester, resulting in troublesome labor for such arrangement.
Normally, therefore, in a repair determination test for determining pass/fail of normal memory cells and spare memory cells performed before fuse blowing, a normal column space and a spare column space are separately tested. By testing the address spaces separately, it is possible to dispense with selector 664 shown in FIG. 25. The normal column space is tested first. The connection of the comparison circuit with the test terminals is then changed over so as not to store fail bits for fixed data in fail bit memory 650 and then the spare column space is tested.
In the test stated above, it is necessary that after the normal column address space is tested, DRAM core 510 is temporarily set in an initial state and test conditions for the spare column address space are set. With the configuration in which memory cell rows are shared by normal memory cells and spare memory cells, it takes disadvantageously long time to perform the test. A total of two times of row select operations are performed to the normal column address space and to the spare column address space.
Further, in the test of the memory cells of DRAM core 510 as stated above, if a data pattern for a memory cell data leakage test is used, data is written to all the normal and spare memory cells once, and the memory cells are kept in a pause state (DRAM core precharged state) for, for example, 64 ms (milliseconds). Then, test is made to examine whether the data stored in these memory cells are lost by leakage current. According to the test pattern for such a data leakage test, even if the spare memory cell space is small such as a space having 16 columns, it is necessary to write the data leakage test pattern to the spare memory cells in the space and to wait for the same time as that for the normal address space. In the memory test for DRAM repair determination, various data patterns, such as the data leakage test pattern, an inter-bit line interference test pattern, a pattern of testing inter-capacitor leakage between the memory cells are used. Therefore, if the normal column address space and the spare column address space are separately tested, test time is disadvantageously lengthened because of this pause time and product cost is disadvantageously increased.